Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a capacitor.
Due to miniaturization of semiconductor memory devices, the area occupied by a capacitor has been reduced due to the decreasing size of a cell. Furthermore, technology to secure a high capacity capacitor is being developed to obtain a capacitor having high capacity for operating a semiconductor device.
Methods for obtaining a high capacity capacitor include expanding the surface area of storage nodes and applying a high-k dielectric layer. There are limitations as to stability and reliability in using a high-k dielectric layer with the existing process. Thus, applying a high-k dielectric layer may not be suitable for a semiconductor device manufacturing process. Therefore, expanding the surface area of storage nodes is more desirable.
Capacitor structures for expanding the surface area of storage nodes include stack structure, concave type, pin type, and cylinder type.
Recently, a cylinder type capacitor that uses a supporter has emerged as a type of a capacitor structure that maximizes the surface area of storage nodes. The supporter is a stabilizing structure which prevents slanting of storage nodes caused by surface tension generated during a subsequent dip out process. A material used as a supporter may also be referred to as a floating layer.
The capacitor having storage nodes fixed by a floating layer may increase capacitance by lengthening the vertical height of the capacitor, and thus expanding the surface area of the storage nodes. Also, the capacitor is a stabilizing structure which prevents slanting of the storage nodes caused by surface tension generated during a subsequent dip out process.
FIGS. 1A to 1E illustrate cross-sectional views of a typical method for fabricating a capacitor.
Referring to FIG. 1A, storage node contact plugs 13 are formed over a substrate 11, and buried in an inter-layer insulation layer 12. An etch stop layer is formed over the storage node contact plugs 13, and a first isolating insulation layer is formed over the etch stop layer. A floating layer is formed over the first isolating insulation layer. The floating layer is formed for use as a supporter. A second isolating insulation layer is formed over the floating layer.
A storage node etching process is performed on a substrate structure to form open regions 18 and exposing surfaces of the storage node contact plugs 13. As a result, etch stop patterns 14, first isolating insulation patterns 15, etched floating layers 16, and second isolating insulation patterns 17 are formed.
Referring to FIG. 1B, a conductive layer is formed over the surface profile of the open regions 18A. A storage node isolation process is performed to form storage nodes 19 having a cylinder form.
Referring to FIG. 1C, a third isolating insulation layer 20 is formed to fill upper portions of open regions 18A formed by the storage nodes 19. A floating capacitor mask 21 is formed over the third isolating insulation layer 20. If the etched floating layers 16 include nitride, the floating capacitor mask 21 may be referred to as a nitride floating capacitor mask.
Referring to FIG. 1D, the third isolating insulation layer 20, the second isolating insulation patterns 17, and the etched floating layers 16 are etched using the floating capacitor mask 21 as an etch barrier. At this time, portions of the storage nodes 19 are also etched. Consequently, a floating pattern 16A is formed to fix adjacent storage nodes 19.
Remaining portions of the second isolating insulation patterns 17, the storage nodes 19, and the third isolating insulation layer 20 are referred to as a remaining second isolating insulation pattern 17A, remaining storage nodes 19A, and a remaining third isolating insulation layer 20A, respectively.
Referring to FIG. 1E, a wet dip out process is performed to remove the first isolating insulation patterns 15 in FIG. 1D. At this time, the remaining third isolating insulation layer 20A and the remaining second isolating insulation pattern 17A are removed at substantially the same time.
However, upper portions of the storage nodes 19 are formed in a sharp shape during the storage node isolation process according to this typical method, as represented by reference denotation ‘A’ shown in FIG. 1B. Such sharp shape is a primary cause of breaking after the subsequent wet dip out process is performed.
Furthermore, after the etched floating layers 16 are etched using this typical method, there is a height difference between portions of the remaining storage nodes 19A formed where the floating pattern 16A remains and other portions of the remaining storage nodes 19A formed where the etched floating layers 16 are etched away, as represented by reference denotation ‘B’ shown in FIG. 1D.
Moreover, the sharp upper portions of the storage nodes 19 are further etched during the etching of the etched floating layers 16, resulting in even sharper upper portions, as represented by reference denotation ‘C’ shown in FIG. 1D. Thus, the remaining storage nodes 19A become more likely to break.
FIG. 2A illustrates a micrographic view showing sharp portions of typical storage nodes, as represented by reference denotation 22. FIG. 2B illustrates a micrographic view showing losses of upper portions of typical storage nodes occurred while etching a floating layer, as represented by reference denotation 23. FIG. 2C illustrates micrographic views showing secondary contamination caused by lost pieces of typical storage nodes, as represented by reference denotation 24.